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THC63LVD104C_rev.2.1_e copyright?2010 thine electronics, inc. 1/13 thine electronics, inc. THC63LVD104C 112mhz 30bits color lvds receiver general description the THC63LVD104C receiver is designed to support pixel data transmission between host and flat panel display from ntsc up to sxga resolutions. the THC63LVD104C converts the lvds data streams back into 35bits of cmos/ttl data with the choice of the rising edge or falling edge clock for the convenience with a variety of lcd pane l controllers.at a transmit clock frequency of 112mhz, 30bits of rgb data and 5bits of timing and control data (hsync, vsync,de,cntl1,cntl2) are transmitted at an effective rate of 784mbps per lvds channel.using a 112mhz clock, the data throughput is 490mbytes per second. features ? wide dot clock range: 8-112mhz suited for ntsc, vga, svga, xga, and sxga ? pll requires no external components ? 50% output clock duty cycle ? ttl clock edge programmable ? power down mode ? low power single 3.3v cmos design ? 64pin tqfp ? backward compatible with thc63lvdf64x (18bits) / f84x(24bits) ? pin compatible with thc63lvd104a ? fail-safe for open lvds input block diagram lvds input cmos/ttl output rclk+/- (8 to 112 mhz) pll ra+/- rb+/- rc+/- rd+/- re+/- test pd oe r/f ra6-ra0 rb6-rb0 rc6-rc0 rd6-rd0 re6-re0 clkout serial to parallel cmos/ttl input 7 7 7 7 7
copyright?2010 thine electronics, inc. 2/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine pin out rb6 clkout gnd rc0 rc1 rc2 rc3 rc4 rc5 vcc rc6 rd0 rd1 rd 2 rd3 rd4 gnd test pd oe r/f re6 re5 re4 vcc re3 re2 re1 re0 rd6 rd5 gnd ra- ra+ rb- rb+ lvcc rc- rc+ rclk- rclk+ lgnd rd- rd+ re- re+ pgnd pvcc vcc ra0 ra1 ra2 gnd ra3 ra4 ra5 ra6 rb0 rb1 vcc rb2 rb3 rb4 rb5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
copyright?2010 thine electronics, inc. 3/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine pin description ** rxn x = a,b,c,d,e n = 0,1,2,3,4,5,6 pin name pin # type description ra+, ra- 50, 49 lvds in lvds data in. rb+, rb- 52, 51 lvds in rc+, rc- 55, 54 lvds in rd+, rd- 60, 59 lvds in re+,re- 62, 61 lvds in rclk+, rclk- 57, 56 lvds in lvds clock in. ra6 ~ ra0 40,41,42 ,43,45,46,47 out cmos/ttl data outputs. rb6 ~ rb0 32,33,34 ,35,36,38,39 out rc6 ~ rc0 22,24,25,26,27,28,29 out rd6 ~ rd0 14,15,17,18,19,20,21 out re6 ~ re0 6,7,8,10,11,12,13 out test 2 in test pin, must be ?l? for normal operation. pd 3 in h: normal operation, l: power down (all outputs are ?l?) oe 4 in h: output enable (normal operation). l: output disable(all outputs are hi-z) r/f 5 in output clock triggering edge select. h: rising edge, l: falling edge vcc 9,23,37,48 power power supply pins for ttl outputs and digital circuitry. clkout 31 out clock out. gnd 1,16,30,44 ground ground pins for ttl outputs and digital circuitry. lvcc 53 power power supply pin for lvds inputs. lgnd 58 ground ground pin for lvds inputs. pvcc 64 power power supply pin for pll circuitry. pgnd 63 ground ground pin for pll circuitry. pd r/f oe data outputs (rxn) clkout 0 0 0 hi-z hi-z 0 0 1 all 0 fixed low 0 1 0 hi-z hi-z 0 1 1 all 0 fixed low 1 0 0 hi-z hi-z 1 0 1 data out the falling edge closer to the center of the data eye. 1 1 0 hi-z hi-z 1 1 1 data out the rising edge closer to the center of the data eye.
copyright?2010 thine electronics, inc. 4/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine absolute maximum ratings 1 electrical characteristics cmos/ttl dc specifications vcc =lvcc=pvcc= 3.0v ~ 3.6v, ta = -20 ~ +85 lvds receiver dc specifications vcc =lvcc=pvcc= 3.0v ~ 3.6v, ta = -20 ~ +85 supply voltage (v cc =vcc=lvcc=pvcc) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) lvds receiver input voltage -0.3v ~ (v cc + 0.3v) output current -30ma ~ 30ma junction temperature +125 storage temperature range -55 ~ +150 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 2.1w 1. ?absolute maximum ratings? are those values beyond which the safety of the device can not be guaranteed. they are not meant to imply that th e device should be operated at these limits. the tables of ?electrical characteristics? specify conditions for device operation. symbol parameter conditions min. typ. max. units v ih high level input voltage 2.0 v cc v v il low level input voltage gnd 0.8 v v oh high level output voltage i oh = -4ma (data) i oh = -8ma (clock) 2.4 v v ol low level output voltage i ol = 4ma (data) i ol = 8ma (clock) 0.4 v i inc input current a symbol parameter conditions min. typ. max. units v th differential inpu t high threshold v ic = 1.2v 100 mv v tl differential input low threshold v ic = 1.2v -100 mv i inl input current v in = 2.4v / 0v v cc = 3.6v 30 a c c c c c c c 0v v in v cc ? 10 c c
copyright?2010 thine electronics, inc. 5/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine supply current vcc =lvcc=pvcc= 3.0v ~ 3.6v, ta = -20 ~ +85 *the trade-off between the output load and the ambient temperature exists so that the junction temperature does not exceed 125 . symbol parameter conditions typ. max. units i rccw receiver supply current (lvds full toggle) f clkout = 75mhz cl=8pf,vcc=3.6v, ta = - 2 0 ~ 8 5 205 ma f clkout = 90mhz 236 ma f clkout = 112mhz cl=8pf,vcc=3.6v, ta = - 2 0 ~ 7 0 * 280 ma i rccs receiver power down supply current pd = l 25 a c c c c c c c clkout rx0 lvds full toggle pattern rx1 rx2 rx3 rx4 rx5 rx6 x=a,b,c,d,e
copyright?2010 thine electronics, inc. 6/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine output load limitation the output load is limited so that the junction temperature does not exceed 125 . c 0.0 5.0 10.0 15.0 20.0 25.0 828486888108 frequency[mhz] output load[pf] ta=70 ta=85
copyright?2010 thine electronics, inc. 7/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine switching characteristics vcc =lvcc=pvcc= 3.0v ~ 3.6v, ta = -20 ~+85 symbol parameter min. typ. max. units t rcp clkout period 8.92 t 125.0 ns t rch clkout high time ns t rcl clkout low time ns t rs ttl data setup to clkout ns t rh ttl data hold from clkout ns t tlh ttl low to high transition time 1.0 3.0 ns t thl ttl high to low transition time 1.0 3.0 ns t sk receiver skew margin clkout=50mhz -1000 0 1000 ps clkout=75mhz -550 0 550 ps clkout=90mhz -400 0 400 ps clkout=112mhz -250 0 250 ps t rip1 input data position0 - t sk 0 + t sk ns t rip0 input data position1 ns t rip6 input data position2 ns t rip5 input data position3 ns t rip4 input data position4 ns t rip3 input data position5 ns t rip2 input data position6 ns t rpll phase lock loop set 10.0 ms t rcd rclk +/- to clkout delay clkout=75mhz 46.5 52.5 ns t rcip clkin period 8.92 125.0 ns c c t 2 --- t 2 --- 4 7 -- -t rcp 1 ? 3 7 -- -t rcp 1 ? t rcip 7 ------------- -t sk ? t rcip 7 ------------- - t rcip 7 ------------- -t sk + 2 t rcip 7 ------------- -t sk ? 2 t rcip 7 ------------- -2 t rcip 7 ------------- -t sk + 3 t rcip 7 ------------- -t sk ? 3 t rcip 7 ------------- -3 t rcip 7 ------------- -t sk + 4 t rcip 7 ------------- -t sk ? 4 t rcip 7 ------------- -4 t rcip 7 ------------- -t sk + 5 t rcip 7 ------------- -t sk ? 5 t rcip 7 ------------- -5 t rcip 7 ------------- -t sk + 6 t rcip 7 ------------- -t sk ? 6 t rcip 7 ------------- -6 t rcip 7 ------------- -t sk +
copyright?2010 thine electronics, inc. 8/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine x = a,b,c,d,e n = 0,1,2,3,4,5,6 vcc/2 r/f = l r/f = h t rcp t rs t rh t rch t rcl clkout rxn vcc/2 vcc/2 vcc/2 vcc/2 ac timing diagrams ttl outputs ttl output ttl output load 20% 80% 20% 80% t tlh t thl c l =8pf
THC63LVD104C_rev.2.1_e copyright?2010 thine electronics, inc. 9/13 thine electronics, inc. ac timing diagrams phase lock loop set time vcc 3.0v 2.0v 2.0v t rpll rclk+/- pd clkout v diff =0v rclk+ rclk +/- to clkout delay current data vcc/2 t rcd current data rxn x = a,b,c,d,e n = 0,1,2,3,4,5,6 note: 1)v diff = (rclk+) - (rclk-) ry+/- y = a,b,c,d,e clkout r/f = l
THC63LVD104C_rev.2.1_e copyright?2010 thine electronics, inc. 10/13 thine electronics, inc. ac timing diagrams v diff = 0v v diff = 0v rclk+ t rip1 t rip0 t rip6 t rip5 t rip4 t rip3 t rip2 lvds inputs re6 re5 re4 re3 re2 re1 re0 re+/- rd6 rd5 rd4 rd3 rd2 rd1 rd0 rd+/- rc6 rc5 rc4 rc3 rc2 rc1 rc0 rc+/- rb6 rb5 rb4 rb3 rb2 rb1 rb0 rb+/- ra6 ra5 ra4 ra3 ra2 ra1 ra0 ra+/- (differential) next cycle previous cycle current cycle re3? re2? re1? re0? rd3? rd2? rd1? rd0? rc3? rc2? rc1? rc0? rb3? rb2? rb1? rb0? ra3? ra2? ra1? ra0? re6?? rd6?? rc6?? rb6?? ra6?? t rcip
copyright?2010 thine electronics, inc. 11/13 thine electronics, inc. THC63LVD104C_rev.2.1_e thine note 1)power on sequence power on lvds-tx after THC63LVD104C. 2)cable connection and disconnection don't connect and disconnect the lvds cable, when the power is supplied to the system. 3)gnd connection connect the each gnd of the pcb wh ich lvds-tx and THC63LVD104C on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 4)multi drop connection multi drop connection is not recommended. 5)asynchronous use asynchronous use such as foll owing systems are not recommended. THC63LVD104C lvds-tx THC63LVD104C tclk+ tclk- THC63LVD104C THC63LVD104C lvds-tx lvds-tx ic clkout clkout data data ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVD104C THC63LVD104C ic tclk+ tclk- tclk+ tclk- clkout data data ic
THC63LVD104C_rev.2.1_e copyright?2010 thine electronics, inc. 12/13 thine electronics, inc. package s seating plane 0.08 m 0.10 1.00 ref. 0.60+/-0.15 0.25mm gage plane 0.20+/-0.03 1.00+/-0.05 0.05~0.15 1.2 max 0.50 bsc. 0.09~0.20 s 3.5+/-3.5 degree 10.00 bsc. 10.00 bsc. 12.00 bsc. 12.00 bsc. unit : mm THC63LVD104C
THC63LVD104C_rev.2.1_e copyright?2010 thine electronics, inc. 13/13 thine electronics, inc. notices and requests 1. the product specifications descri bed in this material are subjec t to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possi ble errors and omissions in this material. please note if errors or omissions should be fo und in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other propr ietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third part y's industrial ownership s hould occur by using this product, we will be exempted fro m the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (including medical equipment direct ly concerning people's life, aerospace equipment, or nuclear control eq uipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after ap plying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small pr obability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign ex change and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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